In recent years, particularly in the field of small-sized portable electronic devices, there has been a movement toward downsizing, high functionality, and high-density mounting of electronic components, which are built in electronic devices. According to such a movement, there has been a demand for small-sized semiconductor packages which contain semiconductor chips.
One example of such small-sized semiconductor packages is a semiconductor package being equal in size to a chip (CSP: Chip Size Package), which is disclosed in Japanese Patent No. 3176542 (publication date: May 6, 1997), for example. In the CSP, generally, electrode pads are disposed in a peripheral part of a semiconductor chip, and electrically connected to an interpose substrate by wire bonding using metal wires (wire connections). Such an arrangement, in which the electrode pads are disposed in the peripheral part of the semiconductor chip, aims to (i) shorten the length of the wires, (ii) prevent deformation of the wire and shorting of the wire due to contact between the wire and the edge of the semiconductor chip, and (iii) facilitate disposing functional elements on the semiconductor chip.
FIG. 4(a) is a perspective view illustrating an exemplary structure of a CSP, and FIG. 4(b) is its cross-sectional view. As shown in the FIGS. 4(a) and 4(b), a CSP 60 includes: an interposer substrate 65; a semiconductor chip 62 mounted on the interposer substrate 65; wires 66 for connecting the interposer substrate 65 and the semiconductor chip 62; and a sealing resin 68 for sealing the semiconductor chip 62 and the wires 66.
The interposer substrate 65 includes an insulating base section 65a, a resist section 65b, and conductive sections 65c. The resist section 65b is provided on a surface of the insulating base section 65a for protecting the surface thereof. Further, each of the conductive sections 65c includes a through hole section and metal pattern sections. Each through hole section, provided in the insulating base section 65a, contains a conductive material, and the metal pattern sections are formed on both surfaces of the insulating base section 65a, respectively. A metal pattern section, formed on one surface of the insulating base section 65a, is connected to an electrode pad 64 on the semiconductor chip 62 using a wire 66. On the other hand, a metal pattern section formed on the other surface is connected to an external connection terminal 67.
One surface of the semiconductor chip 62 is fixed to the interposer substrate 65 via a die bonding sheet 69, and the other surface of the semiconductor chip 62 has electrode pads 64 disposed in its peripheral part. Each of the electrode pads 64 has a bonding connection with one leading end of a wire 66, and the other leading end of the wire 66 has a bonding connection with a conductive section 65c (metal pattern section) of the interposer substrate 65. Further, the other surface of the semiconductor chip 62 is sealed with an insulating layer 63, excluding regions where the electrode pads 64 are disposed. Further, the semiconductor chip 62, the insulating layer 63, the electrode pads 64, and the wires 66 are encapsulated with the sealing resin 68 and thus entirely protected.
With the above structure, in the CSP 60, signals on the semiconductor chip 62 are respectively supplied from the electrode pads 64 to the external connection terminals 67 via wires 66 and the conductive sections 65c of the interposer substrate 65.
Further, another example of the small-sized semiconductor package is a semiconductor package (wafer level CSP) disclosed in Japanese Patent No. 3502056 (publication date: Oct. 18, 2002). Such a semiconductor package is realized by directly forming external connection terminals on a surface of a semiconductor chip, so that the semiconductor chip itself serves as a semiconductor package (wafer level CSP). In the wafer level CSP, rewiring is performed by plating the surface of the semiconductor chip. This provides internal connections between electrode pads of the semiconductor chip and the external connection terminals.
FIG. 5(a) is a perspective view illustrating an exemplary structure of a wafer level CSP, and FIG. 5(b) is its cross-sectional view. In a wafer level CSP 80 shown in FIGS. 5(a) and 5(b), on one surface of a semiconductor chip 82, electrode pads 84 are disposed in its peripheral part, while the rest part of the surface is covered with an insulating layer 83, excluding the regions where the electrode pads 84 are disposed. Further, one end of each conductive section 86, formed by plating, is connected to an electrode pad 84, while the other end of the conductive section 86 is connected to an external connection terminal 87 formed over the insulating layer 83. Further, the surface is covered with an insulating layer 88 and thus protected, excluding regions where external connection terminals 87 are attached (i.e., regions where the insulating layer 83, the electrode pads 84, and the conductive sections 86 are provided).
With the above structure, in the wafer level CSP 80, signals on the semiconductor chip 82 are supplied from the electrode pads 84 to the external connection terminals 87 via the conductive sections 86, respectively.
However, with such conventional wafer level CSP techniques, disposing external connection terminals in the peripheral part as well as in the vicinity of the center part of the semiconductor chip causes a problem of being unable to draw wires from the electrode pads to the external connection terminals in the vicinity of the center part.
When a large number of external connection terminals are provided, the external connection terminals need to be disposed not only in the vicinity of the center part but also in the peripheral part of a semiconductor chip. In a semiconductor chip provided in a conventional wafer level CSP, however, electrode pads are provided in the peripheral part of the semiconductor chip. Thus, disposing external connection terminals in the peripheral part of the semiconductor chip causes the electrode pads to be covered. As a result, wires cannot be drawn from the covered electrode pads.
When external connection terminals need to be disposed also in the peripheral part of a semiconductor chip, it has been therefore necessary to design another semiconductor chip, dedicated to a wafer level CSP, in which electrode pads are disposed not only on a peripheral part but also in an inner part of the semiconductor chip (i.e., an inner part away from the edge of the semiconductor chip). In this case, it is impossible to share a semiconductor package used in a conventional CSP package. This gives rise to a problem of increasing cost and time for development, for example when employing semiconductor packages of a same type for both a wafer level CSP and a CSP.